1. Field of the Invention
The present invention relates to the field of semiconductor packaging, in particular, the technique of tape automated bonding (TAB). More specifically, the present invention relates to packaging a very large scale integration (VLSI) semiconductor die using a tape with land grid array (LGA) outer lead bumps having high precision inter-bump pitches.
2. Background
TAB, including the use of tapes with LGA outer lead bumps, is well known in the art of semiconductor packaging. Typically, springs are provided at the land pattern of the socket to which the semiconductor package is to be tested and burned in, to accommodate the differences in the "heights" of the outer lead bumps. Under today's technology, the technique works well as long as the distances between the springs, and therefore the inter-bump pitches, are not less than 1.2 mm. However, as the scale of integration continues to increase, the number of outer lead bumps required also increases. Unless either the size of the tape is increased or the size of the outer lead bumps are decreased, the inter-bump pitches have to be decreased beyond 1.2 mm. If the inter-bump pitches are decreased beyond 1.2 mm, either a new approach for providing the springs at the land pattern of the socket under the tighter requirement has to be provided, or an alternate approach to address the differences in "heights" of the outer lead bumps has to be provided. Thus, it is desirable to be able to package a VLSI semiconductor die using a tape with LGA outer lead bumps having inter-bump pitches smaller than 1.2 mm, without requiring the corresponding land pattern on the socket to address the differences in "heights" of the outer lead bumps. As will be disclosed, the present invention provides for such a TAB semiconductor package which advantageously achieves the desired results. As described in the copending U.S. patent application, Ser. No. 099,740, filed concurrently, and assigned to the assignee of the present invention, the TAB semiconductor package of the present invention has particular application to packaging upgradable multi-chip modules.